1. Field of the Invention
The present invention relates to a magnetic random access memory (MRAM) using a magneto resistive effect.
2. Description of the Related Art
A magnetic random access memory using a tunneling magneto resistive (TMR) effect is described, for example, in Patent Documents 1 to 3 and Non-Patent Documents 1 to 5. These magnetic random access memories are characterized in that data is stored by a magnetized state of a magnetic tunnel junction (MTJ) element.
(1) The data is stored by the magnetized state of the MTJ element as described above in the magnetic random access memory. Therefore, the magnetized state of the MTJ element has to be changed in accordance with a value of written data at a write time.
Here, a configuration of the MTJ element capable of realizing enhancement of a resistance to disturbance has been researched in order to prevent a write error at a write time. At present, it has been confirmed that when the MTJ element is formed in a “cross type”, the resistance to disturbance can be enhanced.
However, the MTJ element itself has become very minute in order to realize a large memory capacity. Therefore, for example, when a pattern for the MTJ element is to be formed using a photolithography technique, contour becomes blurred, and a complete cross shape cannot be obtained.
Additionally, concerning the photolithography technique, it is also possible to form the pattern of the MTJ element by application of the lithography technique of the next generation, having a resolution higher than that realized in the present generation, in an experimental, trial production stage.
However, in an actual mass production stage, it is necessary to select the photolithography technique having an optimum resolution from aspects of cost, yield and the like at this time. Therefore, it is impossible to process the MTJ element constantly by the application of a most advanced photolithography technique.
(2) According to the cross type MTJ element, an effect of enhancement of resistance to disturbance can be obtained, but several problems have to be overcome in order to realistically achieve the effect.
For example, concerning a positional relation between a pinned layer (fixed layer) and a free layer (recording layer) of the MTJ element, two types have been known: a bottom pin structure in which the pinned layer is positioned down and the free layer is positioned up with a silicon substrate side down; and a top pin structure in which the pinned layer is positioned up and the free layer is positioned down.
Here, with use of the former bottom pin structure, the pinned layer can be formed in a tetragonal shape, and therefore there is little leak magnetic field from the pinned layer, and fluctuations of a magnetic field between the MTJ elements can be eliminated, but there is a problem that characteristics of a magnetic layer cannot be enhanced.
Moreover, with the use of the latter top pin structure, it is possible to obtain an advantage that the characteristics of the magnetic layer can be enhanced. However, since the pinned layer is also formed in a cross type, the leak magnetic field from the pinned layer becomes remarkably non-uniform, and a problem occurs that the fluctuations of the magnetic field between the MTJ elements are also increased because of fluctuations of the shape of the MTJ element.
Patent Documents 1 to 3 and Non-Patent Documents 1 to 5 are as follows:
Patent Document 1: Jpn. Pat. Appln. KOKAI
Publication No. 2002-170376;
Patent Document 2: U.S. Pat. No. 6,545,906;
Patent Document 3: U.S. Pat. No. 6,081,445;
Non-Patent Document 1: M. Durlam et al. “A Low Power 1 Mbit MRAM based on 1T1M TJ Bit Cell integrated with Copper Interconnects”, IEEE, 2002 Symposium on VLSI Circuits Digest of Technical Papers;
Non-Patent Document 2: T. HONDA et al. “MRAM-Writing Circuitry to compensate for Thermal-Variation of Magnetization-Reversal Current”, 2002 Symposium on VLSI Circuits Digest of Technical Papers, pp. 156 to 157, July 2002;
Non-Patent Document 3: Roy Scheuerlein et al. “A 10 ns Read and Write Nonvolatile Memory Array using a Magnetic Tunnel Junction and FET Switch in each Cell”, ISSCC2000 Technical Digest, pp. 128 to 129;
Non-Patent Document 4: A Bette et al. “A High-Speed 128 Kbit MRAM Core for Future Universal Memory Applications”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, pp. 217 to 220, July 2003; and
Non-Patent Document 5: A. R. Sitaram et al. “A 0.18 um Logic-based MRAM Technology for High Performance Nonvolatile Memory Applications”, 2003 Symposium on VLSI Circuits Digest of Technical Papers, 0.14, July 2003.